SilverStone ST50F-ES [8/12] Manual st50f es p202 v1 5

4.1 Signal timing drawing

4.2 .Output Transient Response

( 1 )T2: Rise time (0.1ms~20ms)

( 2 )T3: Power good turn on delay time (100ms~500ms)

( 3 )T4: Power good turn off delay time (1ms min)

( 4 )T5: Rise time (10ms max)

Figure 4 is a reference for signal timing for main power connector signals and rails.

Table 13. summarizes the expected output transient step sizes for each output.

The transient load slew rate is =1.0A/us.

Table 13. DC Output Transient Step Sizes

(1) For example, for a rated +5 VDC output of 18A,the transient step would be 30% x 18A=5.4A

Output voltages should remin within the remain within the regulation limits of Section 2.1,and the

power supply should stable when subjected to load transients per Table 13. from any steady state

load, including any or all of the following conditions:

Max.step size Max.step size

(% of rated output amps per Sec 3.2.3) (amps)

+12 VDC 40% 　 -

+5 VDC 30% 　 -

+3.3 VDC 30% -　

-12 VDC 　 - 0.1A

+5 VSB 　 - 0.5A

Output

4. TIMING