MSI Z77A-GD80 [64/100] Bios setup

2-14

BIOS Setup

tRAS

Determnes the tme RAS (row address strobe) takes to read from and wrte to mem

ory cell.

tRFC

Ths settng determnes the tme RFC takes to read from and wrte to a memory

cell.

tWR

Determnes mnmum tme nterval between end of wrte data burst and the start of a

pre-charge command. Allows sense amplers to restore data to cell.

tWTR

Determnes mnmum tme nterval between the end of wrte data burst and the start

of a column-read command; allows I/O gatng to overdrve sense amples before

read command starts.

tRRD

Speces the actve-to-actve delay of derent banks.

tRTP

Tme nterval between a read and a precharge command.

tFAW

Ths tem s used to set the tFAW (four actvate wndow delay) tmng.

tWCL

Ths tem s used to set the tWCL (Wrte CAS Latency) tmng.

tCKE

Ths tem s used to set the Pulse Wdth for DRAM module.

tRTL

Ths tem s used to set Round Trp Latency settngs.

Advanced Tmng Conguraton

Press <Enter> to enter the sub-menu. And you can set the advanced memory tmng

for each channel.

tRRDR

Speces the actve-to-actve delay of derent ranks on the same DIMM.

tRRDD

Speces the actve-to-actve delay of derent DIMMs.

tWWDR

Speces the wrte-to-wrte delay of derent ranks on the same DIMM.

tWWDD

Speces the wrte-to-wrte delay of derent DIMMs.

tRWDRDD

Speces the read-to-wrte delay of derent ranks on the same/ derent DIMM(s).

▶