ASRock Beebox Series (Apollo Lake) — настройка DRAM: Оптимизация параметров памяти для производительности [34/55]

Превью страниц Страница 34 / 55

28 29

English

DRAM Conguration

DRAM Tweaker

Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to conrm and

apply your new settings.

DRAM Timing Conguration

CAS# Latency (tCL)

e time between sending a column address to the memory and the beginning of the data

in response.

RAS# to CAS# Delay and Row Precharge (tRCDtRP)

RAS# to CAS# Delay : e number of clock cycles required between the opening of

a row of memory and accessing columns within it.

Row Precharge: e number of clock cycles required between the issuing of the

precharge command and opening the next row.

RAS# Active Time (tRAS)

e number of clock cycles required between a bank active command and issuing the

precharge command.

Command Rate (CR)

e delay between when a memory chip is selected and when the rst active command can

be issued.

Refresh Cycle Time (tRFC)

e number of clocks from a Refresh command until the rst Activate command to

the same rank.

Save User Default

Type a prole name and press enter to save your settings as user default.