ASRock B760M Steel Legend WiFi [41/97] Intel z790 h770 b760 series

Intel Z790/H770/B760 Series

Row Precharge (tRP)

e number of clock cycles required between the issuing of the precharge command and

opening the next row.

RAS# Active Time (tRAS)

e number of clock cycles required between a bank active command and issuing the

precharge command.

Command Rate (CR)

e delay between when a memory chip is selected and when the rst active command

can be issued.

Secondary Timing

Write Recovery Time (tWR)

e amount of delay that must elapse aer the completion of a valid write operation,

before an active bank can be precharged.

Refresh Cycle Time 2 (tRFC2)

e number of clocks from a Refresh command until the rst Activate command to the

same rank.

Refresh Cycle Time per Bank (tRFCpb)

e number of clocks from a Refresh command (per bank) until the rst Activate

command to the same rank.

RAS to RAS Delay (tRRD_L)

e number of clocks between two rows activated in dierent banks of the same rank.

RAS to RAS Delay (tRRD_S)

e number of clocks between two rows activated in dierent banks of the same rank.

Write to Read Delay (tWTR_L)

e number of clocks between the last valid write operation and the next read command

to the same internal bank.

Write to Read Delay (tWTR_S)

e number of clocks between the last valid write operation and the next read command

to the same internal bank.