ASRock B760M-HDV/M.2 D4 [46/97] Round trip timing optimization

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tWRWR_dr

Congure between module write to write delay.

Conguration options: [Auto] [0] - [127]

tWRWR_dd

Congure between module write to write delay.

Conguration options: [Auto] [0] - [255]

Round Trip Timing

Round Trip Timing Optimization

Auto is enabled in general case.

Conguration options: [Auto] [Enabled] [Disabled]

Round Trip Level

Congure round trip level.

Conguration options: [Tightest] [Tighter] [Tight] [Normal] [Loose] [Looser] [Loosest]

Initial RTL IO Delay Oset

Congure round trip latency IO delay initial oset.

Initial RTL FIF0 Delay Oset

Congure round trip latency FIF0 delay initial oset.

Initial RTL (MC0 C0 A1/A2)

Congure round trip latency initial value.

Initial RTL (MC0 C1 A1/A2)

Congure round trip latency initial value.

Initial RTL (MC1 C0 B1/B2)

Congure round trip latency initial value.

Initial RTL (MC1 C1 B1/B2)

Congure round trip latency initial value.

RTL (MC0 C0 A1/A2)

Congure round trip latency.