Acer Iconia Tab W701 i5 64Gb [12/52] Channel b

Acer Iconia Tab W701 i5 64Gb [12/52] Channel b
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Layout Note:
Place near each memory part
Channel B
DDR3 CLK Termination
1.CAD Note: Cterm= 1.8pF should be kept
near feeding point of first SDRAM
2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF
should be kept within 600mils from last SDRAM
END topology
DDR3 CTL/ADD Termination
SAGE 3GSAGE 3GSAGE 3GSAGE 3G
SAGE 3G
SAGE 3G
SAGE 3G
SAGE 3G
SAGE 3G SAGE 3G SAGE 3G SAGE 3G
SAGE 3G PVT SAGE 3G PVT SAGE 3G PVT SAGE 3G PVT
SAGE 3G PVT
DDR_B_CS0#
DDR_B_ODT0 DDR_B_ODT0
DDR_B_CS0#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_CLK0
DDR_B_CKE0
DDR_B_CLK0#
DDR_B_CLK0
DDR_B_CKE0
DDR_B_CLK0#
DDR_B_MA4
DDR_B_MA6
DDR_B_DQS5
DDR_B_MA11
DDR_B_MA14
DIMM_DRAMRST#
DDR_B_MA0
DDR_B_MA7
DDR_B_DQS#5
DDR_B_BS1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_MA2
DIMM_DRAMRST#
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_MA14
DDR_B_MA11
DDR_B_MA6
DDR_B_MA4
DDR_B_BS1
DDR_B_MA7
DDR_B_MA0
DDR_B_RAS#
DDR_B_MA2
DDR_B_ODT0
DDR_B_CS0#
DDR_B_MA8
DDR_B_BS2
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9
DDR_B_MA12
DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA13
DDR_B_MA4
DDR_B_MA6
DDR_B_MA11
DDR_B_MA14
DIMM_DRAMRST#
DDR_B_RAS#
DDR_B_MA0
DDR_B_MA7
DDR_B_BS1
DDR_B_MA2
DDR_B_CLK0
DDR_B_CKE0
DDR_B_CLK0#
DDR_B_MA8
DDR_B_BS2
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9
DDR_B_MA12
DDR_B_BS0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA13
DDR_B_CAS#
DDR_B_WE#
DDR_B_MA6
DDR_B_MA4
DDR_B_MA7
DDR_B_MA0
DDR_B_RAS#
DIMM_DRAMRST#
DDR_B_MA14
DDR_B_MA11
DDR_B_BS1
DDR_B_MA2
DDR_B_BS2
DDR_B_MA8
DDR_B_BS0
DDR_B_MA12
DDR_B_MA9
DDR_B_MA5
DDR_B_MA3
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_MA1
DDR_B_MA10
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_BS2
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_MA12
DDR_B_MA9
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_ODT0
DDR_B_CS0#
DDR_B_CLK0
DDR_B_CKE0
DDR_B_CLK0#
DDR_B_MA15 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15
DDR_B_DQS7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_D55
DDR_B_D49
DDR_B_D52
DDR_B_D51
DDR_B_D53
DDR_B_D50
DDR_B_D48
DDR_B_D54
DDR_B_D5
DDR_B_D3
DDR_B_D0
DDR_B_D1
DDR_B_D6
DDR_B_D4
DDR_B_D7
DDR_B_D2
DDR_B_D23
DDR_B_D16
DDR_B_D21
DDR_B_D22
DDR_B_D18
DDR_B_D17
DDR_B_D19
DDR_B_D20
DDR_B_D34
DDR_B_D33
DDR_B_D36
DDR_B_D38
DDR_B_D39
DDR_B_D37
DDR_B_D35
DDR_B_D32
DDR_B_D14
DDR_B_D12
DDR_B_D8
DDR_B_D11
DDR_B_D15
DDR_B_D13
DDR_B_D9
DDR_B_D10
DDR_B_D24
DDR_B_D31
DDR_B_D26
DDR_B_D29
DDR_B_D25
DDR_B_D30
DDR_B_D27
DDR_B_D28
DDR_B_D40
DDR_B_D47
DDR_B_D45
DDR_B_D46
DDR_B_D41
DDR_B_D43
DDR_B_D44
DDR_B_D42
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D59
DDR_B_D63
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_MA8
DDR_B_MA9
DDR_B_MA5
DDR_B_MA13
DDR_B_MA0
DDR_B_MA4
DDR_B_MA11
DDR_B_MA14
DDR_B_BS1
DDR_B_MA15
DDR_B_CS0#
DDR_B_ODT0
DDR_B_CKE0
DDR_B_RAS#
DDR_B_CAS#
DDR_B_BS0
DDR_B_MA10
DDR_B_WE#
DDR_B_BS2
DDR_B_MA7
DDR_B_MA6
DDR_B_MA1
DDR_B_MA3
DDR_B_MA12
DDR_B_MA2
DDR_B_CKE1
DDR_B_CS1#
DDR_B_ODT1
DDR_B_CS1#
DDR_B_CKE1
DDR_B_ODT1
DDR_B_CS1#
DDR_B_CKE1
DDR_B_ODT1
DDR_B_CS1#
DDR_B_CKE1
DDR_B_ODT1
DDR_B_CS1#
DDR_B_CKE1
DDR_B_ODT1
DDR_B_MA[0..15] 6
DDR_B_DQS#[0..7] 6
DDR_B_DQS[0..7] 6
DDR_B_D[0..63] 6
DIMM_DRAMRST#11,6
DDR_B_CLK0#6
DDR_B_CLK06
DDR_B_ODT0 6
DDR_B_CKE0 6
DDR_B_RAS# 6
DDR_B_CAS# 6
DDR_B_BS0 6
DDR_B_WE# 6
DDR_B_BS2 6
DDR_B_CS0# 6
DDR_B_BS1 6
DDR_B_CKE1 6
DDR_B_CS1# 6
DDR_B_ODT1 6
+1.35V+1.35V
+VREFDQ_B
+VREFCA_B+VREFCA_B
+VREFDQ_B
+VREFCA_B
+VREFDQ_B+VREFDQ_B
+VREFCA_B
+1.35V +1.35V
+0.675VS
+1.35V
+1.35V
+0.675VS
+VREFCA_B
+1.35V
+VREFDQ_B
+1.35V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
V1JB1 M/B LA-A041P Schematic
0.1
DDRIII DIMMB
Custom
12 52Wednesday, March 13, 2013
2011/06/24 2012/06/02
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
V1JB1 M/B LA-A041P Schematic
0.1
DDRIII DIMMB
Custom
12 52Wednesday, March 13, 2013
2011/06/24 2012/06/02
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
V1JB1 M/B LA-A041P Schematic
0.1
DDRIII DIMMB
Custom
12 52Wednesday, March 13, 2013
2011/06/24 2012/06/02
Compal Electronics, Inc.
C1291
2.2U_0603_6.3V6K
@
C1291
2.2U_0603_6.3V6K
@
12
R1012
240_0402_1%
128@
R1012
240_0402_1%
128@
1 2
C1508
0.1U_0402_16V4Z
128@
C1508
0.1U_0402_16V4Z
128@
1
2
C1490
10U_0603_6.3V6M
@
C1490
10U_0603_6.3V6M
@
12
R1119
1K_0402_1%
128@
R1119
1K_0402_1%
128@
12
96-BALL
SDRAM DDR3
U61
H5TQ2G63BFR-11C_FBGA96
X76@
96-BALL
SDRAM DDR3
U61
H5TQ2G63BFR-11C_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
R1009
240_0402_1%
128@
R1009
240_0402_1%
128@
1 2
C1300
0.1U_0402_16V4Z
128@
C1300
0.1U_0402_16V4Z
128@
1
2
C1488
1U_0402_6.3V6K
@
C1488
1U_0402_6.3V6K
@
12
RP38
36_8P4R_5%128@
RP38
36_8P4R_5%128@
1 8
2 7
3 6
4 5
C1292
2.2U_0603_6.3V6K
@
C1292
2.2U_0603_6.3V6K
@
12
C1298
0.1U_0402_16V4Z
128@
C1298
0.1U_0402_16V4Z
128@
1
2
96-BALL
SDRAM DDR3
U62
H5TQ2G63BFR-11C_FBGA96
X76@
96-BALL
SDRAM DDR3
U62
H5TQ2G63BFR-11C_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
R1005
240_0402_1%
128@R1005
240_0402_1%
128@
1 2
C1293
2.2U_0603_6.3V6K
@
C1293
2.2U_0603_6.3V6K
@
12
C1296
0.1U_0402_16V4Z
128@
C1296
0.1U_0402_16V4Z
128@
1
2
R1120
1K_0402_1%
128@
R1120
1K_0402_1%
128@
12
R1007
240_0402_1%
128@R1007
240_0402_1%
128@
1 2
C1507
2.2U_0603_6.3V6K
128@
C1507
2.2U_0603_6.3V6K
128@
12
RP39
36_8P4R_5%128@
RP39
36_8P4R_5%128@
1 8
2 7
3 6
4 5
R1117
30.1_0402_1%
128@
R1117
30.1_0402_1%
128@
12
C1496
10U_0603_6.3V6M
@
C1496
10U_0603_6.3V6M
@
12
R1118
30.1_0402_1%
128@
R1118
30.1_0402_1%
128@
12
96-BALL
SDRAM DDR3
U63
H5TQ2G63BFR-11C_FBGA96
X76@
96-BALL
SDRAM DDR3
U63
H5TQ2G63BFR-11C_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
R1123
1K_0402_1%
128@
R1123
1K_0402_1%
128@
12
C1497
1U_0402_6.3V6K
@
C1497
1U_0402_6.3V6K
@
12
C1297
0.1U_0402_16V4Z
128@
C1297
0.1U_0402_16V4Z
128@
1
2
R339 36_0201_1%
128@
R339 36_0201_1%
128@
1 2
RP40
36_8P4R_5%128@
RP40
36_8P4R_5%128@
1 8
2 7
3 6
4 5
R1006
240_0402_1%
128@R1006
240_0402_1%
128@
1 2
R390 36_0201_1%
128@
R390 36_0201_1%
128@
1 2
R1010
240_0402_1%
128@
R1010
240_0402_1%
128@
1 2
C1500
10U_0603_6.3V6M
@
C1500
10U_0603_6.3V6M
@
12
C1301
0.1U_0402_16V4Z
128@
C1301
0.1U_0402_16V4Z
128@
1
2
RP41
36_8P4R_5%128@
RP41
36_8P4R_5%128@
1 8
2 7
3 6
4 5
96-BALL
SDRAM DDR3
U60
H5TQ2G63BFR-11C_FBGA96
X76@
96-BALL
SDRAM DDR3
U60
H5TQ2G63BFR-11C_FBGA96
X76@
WE
L3
RAS
J3
CAS
K3
CS/CS0
L2
CKE/CKE0
K9
CK
J7
CK
K7
DQSU
B7
BA0
M2
BA1
N8
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
VSSQ
D1
VSS
A9
VSS
E1
VSS
B3
NC/ODT1
J1
VDD
B2
VDD
D9
VDDQ
A1
VDDQ
A8
VDDQ
C1
VDDQ
C9
NC/CS1
L1
NC/CE1
J9
VDDQ
E9
ZQ/ZQ0
L8
RESET
T2
DQSL
F3
DMU
D3
DML
E7
VSSQ
B1
VSSQ
B9
VSSQ
D8
VSSQ
E2
DQSU
C7
VSSQ
E8
DQSL
G3
VDDQ
F1
VSSQ
F9
VSSQ
G1
VDDQ
H2
VDDQ
H9
VSSQ
G9
VREFCA
M8
VSS
G8
VDD
G7
ODT/ODT0
K1
A0
N3
A1
P7
VDD
K2
A12
N7
VSS
J2
VDD
K8
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
DQU0
D7
A13
T3
A14
T7
A15/BA3
M7
BA2
M3
VREFDQ
H1
NCZQ1
L9
VDD
N1
VDD
N9
VDD
R1
VDD
R9
VSS
J8
VSS
M1
VSS
M9
VSS
P1
VSS
P9
VSS
T1
VSS
T9
VDDQ
D2
C1505
1.8P_0402_50V8
128@
C1505
1.8P_0402_50V8
128@
1
2
R1008
240_0402_1%
128@R1008
240_0402_1%
128@
1 2
C1498
1U_0402_6.3V6K
@
C1498
1U_0402_6.3V6K
@
12
C1504
1U_0402_6.3V6K
@
C1504
1U_0402_6.3V6K
@
12
R340 36_0201_1%
128@
R340 36_0201_1%
128@
1 2
C1510
0.1U_0402_16V4Z
128@
C1510
0.1U_0402_16V4Z
128@
1
2
C1501
1U_0402_6.3V6K
@
C1501
1U_0402_6.3V6K
@
12
R1121
1K_0402_1%
128@
R1121
1K_0402_1%
128@
12
C1503
1U_0402_6.3V6K
@
C1503
1U_0402_6.3V6K
@
12
R342 36_0201_1%
128@
R342 36_0201_1%
128@
1 2
RP37
36_8P4R_5%128@
RP37
36_8P4R_5%128@
1 8
2 7
3 6
4 5
C1502
1U_0402_6.3V6K
@
C1502
1U_0402_6.3V6K
@
12
C1302
2.2U_0603_6.3V6K
@
C1302
2.2U_0603_6.3V6K
@
12
C1295
0.1U_0402_16V4Z
128@
C1295
0.1U_0402_16V4Z
128@
1
2
C1485
10U_0603_6.3V6M
@
C1485
10U_0603_6.3V6M
@
12
C1509
2.2U_0603_6.3V6K
128@
C1509
2.2U_0603_6.3V6K
128@
12
R1011
240_0402_1%
128@
R1011
240_0402_1%
128@
1 2
C1506
0.1U_0402_16V4Z
128@ C1506
0.1U_0402_16V4Z
128@
1 2
RP36
36_8P4R_5%128@
RP36
36_8P4R_5%128@
1 8
2 7
3 6
4 5
C1299
0.1U_0402_16V4Z
128@
C1299
0.1U_0402_16V4Z
128@
1
2
C1487
1U_0402_6.3V6K
@
C1487
1U_0402_6.3V6K
@
12
C1294
0.1U_0402_16V4Z
128@
C1294
0.1U_0402_16V4Z
128@
1
2

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What is the document number of the LA-A041P MB Rev2?
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