ASRock p85 pro3 [52/78] Cas write latency tcwl

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Write Recovery Time (tWR)

e amount of delay that must elapse aer the completion of a valid write operation,

before an active bank can be precharged.

Refresh Cycle Time (tRFC)

e number of clocks from a Refresh command until the rst Activate command to

the same rank.

RAS to RAS Delay (tRRD)

e number of clocks between two rows activated in dierent banks of the same

rank.

Write to Read Delay (tWTR)

e number of clocks between the last valid write operation and the next read

command to the same internal bank.

Read to Precharge (tRTP)

e number of clocks that are inserted between a read command to a row pre-

charge command to the same rank.

Four Activate Window (tFAW)

e time window in which four activates are allowed the same rank.

CAS Write Latency (tCWL)

Congure CAS Write Latency.

tREFI

Congure refresh cycles at an average periodic interval.

tCKE

Congure the period of time the DDR3 initiates a minimum of one refresh

command internally once it enters Self-Refresh mode.

tRDRD

Congure between module read to read delay.

tRDRDDR

Congure between module read to read delay from dierent ranks.

tRDRDDD