MSI B75MA-G43 [52/76] Bios setup

MSI B75MA-G43 [52/76] Bios setup
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BIOS Setup
My OC Gene
Ths tem s used to select whether OC Gene parameters are customzed by user.
Settng to [MSI] OC Gene wll use default OC related parameters to overclock the
system. Selectng [Customze] allows you to congure the followng related “My OC
Gene opton” sub-menu manually for OC Gene.
My OC Gene opton
Press <Enter> to enter the sub-menu.
My OC Gene GT Overclockng
Ths tem allows you to enable/ dsable the overclockng of ntegrated graphcs for
My OC Gene functon.
My OC Gene GT Rato
Ths tem allows you to specc the GT rato for My OC Gene functon.
Adjusted My OC Gene GT Frequency
It shows the GPU frequency when OC Gene s started. Read-only.
DRAM Reference Clock
Ths tem allows you to specc the DRAM Reference Clock for CPU. Please note the
overclockng behavor s not guaranteed.
DRAM Frequency
Ths tem allows you to adjust the DRAM frequency. Please note the overclockng
behavor s not guaranteed.
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect) EE
-
PROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the followng
“Advanced DRAM Conguraton” sub-menu to be determned by BIOS based on the
conguratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to congure the
DRAM tmngs for each channel and the followng related “Advanced DRAM Congura-
ton” sub-menu manually.
Advanced DRAM Conguraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Controls CAS latency whch determnes the tmng delay (n clock cycles) of startng
a read command after recevng data.
tRCD
Determnes the tmng of the transton from RAS (row address strobe) to CAS (col
-
umn address strobe). The less clock cycles, the faster the DRAM performance.
tRP
Controls number of cycles for RAS (row address strobe) to be allowed to pre-charge.
If nsucent tme s allowed for RAS to accumulate before DRAM refresh, the DRAM

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