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OLIMEX A33-OLINUXINO-N8G [6/35] Cpu architecture
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A33 Datasheet
Copyright © 2014 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 6
Features
2
FEATURES
2.1. CPU Architecture
The A33 platform is based on quad-core Cortex
TM
-A7 CPU architecture.
● ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
● NEON with SIMD and VFPv4 support
● Support hardware virtualization
● Support LPAE
● Support 4GB address space
● Support 256KB L1 cache and shared 512KB L2 cache
● Support DVFS with independent power domain
2.2. GPU
● Mali400MP2 GPU
● Support OpenGL ES 2.0 / OpenVG 1.1 standard
Содержание
- Allwinner a33 1
- Datasheet 1
- Quad core tablet processor 1
- Declaration 2
- Revision history 3
- Chapter 1 overview 4
- Chapter 2 features 4
- Chapter 3 block diagram 6 4
- Chapter 4 pin description 17 4
- Chapter 5 electrical characteristics 9 4
- Chapter 6 pin assignment 3 4
- Table of contents 4
- Overview 5
- Cpu architecture 6
- Features 6
- Memory subsystem 7
- System peripheral 8
- Security system 2 9
- Display subsystem 10
- Video engine 11
- Audio subsystem 12
- Video input 12
- External peripherals 13
- Package 15
- Power management 15
- A33 block diagram 16
- Block diagram 16
- And buffer strength 17
- Default pull up down 17
- Following table describes the a33 pin characteristics from seven aspects ball pin name default function 17
- Pin characteristics 17
- Pin description 17
- Reset state 17
- Ball pin name default 18
- Function type reset state default pull up down buffer strength ma 18
- Pin description 18
- Ball pin name default 19
- Function type reset state default pull up down buffer strength ma 19
- Pin description 19
- Ball pin name default 20
- Function type reset state default pull up down buffer strength ma 20
- Pin description 20
- Ball pin name default 21
- Function type reset state default pull up down buffer strength ma 21
- Pin description 21
- Ball pin name default 22
- Function type reset state default pull up down buffer strength ma 22
- Pin description 22
- Following table provides a description of the gpio multiplexing functions of a33 23
- Function io type default io state default pull up down multiplexed function 2 multiplexed function 3 multiplexed function 4 23
- Gpio multiplexing functions 23
- Pin description 23
- Port default 23
- Pin description 24
- Description 25
- Detailed pin signal description 25
- Pin description 25
- Pin signal 25
- Description 26
- Pin description 26
- Pin signal 26
- Description 27
- Detailed pin signal description 27
- Pin description 27
- Pin signal 27
- Description 28
- Pin description 28
- Pin signal 28
- Absolute maximum ratings 29
- Electrical characteristics 29
- Functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied exposure to absolute maximum rated conditions for extended periods may af fect device reliability 29
- Recommended operating conditions 29
- Symbol parameter min max unit 29
- Symbol parameter min typ max unit 29
- 24mhz oscillator characteristics 30
- Dc electrical characteristics 30
- Electrical characteristics 30
- Min typ max unit 30
- Oscillator electrical characteristics 30
- Symbol parameter 30
- Symbol parameter min typ max unit 30
- The 24mhz frequency is used to generate the main source clock of the a33 device 30
- The 32768hz frequency is used for low frequency operation 30
- The a33 contains two oscillators a 24mhz oscillator and a 32768hz oscillator each oscillator requires a specific crystal 30
- The a33 device operation requires following two input clocks 30
- 32768hz oscillator characteristics 31
- Electrical characteristics 31
- Hz oscillator characteristics 31
- Mhz oscillator characteristics 31
- Power up down sequence 31
- Symbol parameter min typ max unit 31
- The 24mhz crystal is connected between the hosci amplifier input and hosco amplifier output 31
- The 32768hz crystal is connected between the losci amplifier input and losco amplifier output 31
- Electrical characteristics 32
- Power up down sequence 32
- The external voltage regulator and other power on devices must provide the processor with a specific sequence of power and resets to ensure proper operations 32
- Pin assignment 33
- Pin map 33
- Package dimension 34
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