RME ADI-6432 REDUNDANT BNC [19/40] Operation and technical background

User's Guide ADI-6432R BNC © RME

11.2 Operation and Technical Background

In the analog domain one can connect any device to another device, synchronization is not

necessary. Digital audio is different. It uses a clock, the sample frequency. The signal can only

be processed and transmitted when all participating devices share the same clock. If not, the

signal will suffer from wrong samples, distortion, crackle sounds and drop outs.

AES/EBU, SPDIF, ADAT and MADI are self-clocking, an additional word clock connection in

principle isn't necessary. But when using more than one device simultaneously problems are

likely to happen. For example any self-clocking will not work in a loop cabling, when there is no

'master' (main clock) inside the loop. Additionally the clock of all participating devices has to be

synchronous. This is often impossible with devices limited to playback, for example CD players,

as these have no SPDIF input, thus can't use the self clocking technique as clock reference.

In a digital studio synchronisation is maintained by connecting all devices to a central sync

source. For example the mixing desk works as master and sends a reference signal, the word

clock, to all other devices. Of course this will only work as long as all other devices are

equipped with a word clock or sync input, thus being able to work as slave (some professional

CD players indeed have a word clock input). Then all devices get the same clock and will work

in every possible combination with each other.

Remember that a digital system can only have one master! If the ADI-6432’s uses its inter-

nal clock, all other devices must be set to ‘Slave’ mode.

But word clock is not only the 'great problem solver', it also has some disadvantages. The word

clock is based on a fraction of the really needed clock. For example SPDIF: 44.1 kHz word

clock (a simple square wave signal) has to be multiplied by 256 inside the device using a spe-

cial PLL (to about 11.2 MHz). This signal then replaces the one from the quartz crystal. Big

disadvantage: because of the high multiplication factor the reconstructed clock will have great

deviations called jitter. The jitter of a word clock is much higher as when using a quartz based

clock.

The end of these problems should have been the so called Superclock, which uses 256 times

the word clock frequency. This equals the internal quartz frequency, so no PLL for multiplying is

needed and the clock can be used directly. But reality was different, the Superclock proved to

be much more critical than word clock. A square wave signal of 11 MHz distributed to several

devices - this simply means to fight with high frequency technology. Reflections, cable quality,

capacitive loads - at 44.1 kHz these factors may be ignored, at 11 MHz they are the end of the

clock network. Additionally it was found that a PLL not only generates jitter, but also rejects

disturbances. The slow PLL works like a filter for induced and modulated frequencies above

several kHz. As the Superclock is used without any filtering such a kind of jitter and noise sup-

pression is missing.

The actual end of these problems is offered by the SteadyClock technology of the ADI-6432.

Combining the advantages of modern and fastest digital technology with analog filter tech-

niques, re-gaining a low jitter clock signal of 22 MHz from a slow word clock of 44.1 kHz is no

problem anymore. Additionally, jitter on the input signal is highly rejected, so that even in real

world usage the re-gained clock signal is of highest quality.