MSI 990XA-GD55 [38/138] Ms 7640 ma nboard

MSI 990XA-GD55 [38/138] Ms 7640 ma nboard
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MS-7640 Manboard
DRAM Frequency
Ths tem s used to adjust the DRAM frequency. Settng to [Auto], the system wll detect
the DRAM Frequency automatcally.
Adjusted DRAM Frequency
It shows the adjusted Memory frequency. Read-only.
DRAM Tmng Mode
Ths eld has the capacty to automatcally detect the DRAM tmng.
Advanced DRAM Conguraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsucent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
tRTP
Tme nterval between a read and a precharge command.
tRC
The row cycle tme determnes the mnmum number of clock cycles a memory row
takes to complete a full cycle, from row actvaton up to the prechargng of the actve
row.
tWR
Mnmum tme nterval between end of wrte data burst and the start of a precharge
command. Allows sense amplers to restore data to cells.
tRRD
Speces the actve-to-actve delay of derent banks.
tWTR
Mnmum tme nterval between the end of wrte data burst and the start of a column-
read command. It allows I/O gatng to overdrve sense amplers before read
command starts.

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