Biostar TA880G+ Версия 5.x [37/46] Dram timing configuration
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Biostar TA880G+ Версия 5.x [37/46] Dram timing configuration

Biostar TA880G+ Версия 5.x [37/46] Dram timing configuration
TA785G3 HD/ TA880G+ BIOS Manual
36
DRAM Timing Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 198 5-200x, American Megatre nds, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
DRAM Timing Config uration
Memory CLK :
CAS Latency(Tcl) :
RAS/CAS Delay(Tr cd) :
Row Precharge Ti me(Trp):
Min Active RAS(T ras) :
RAS/RAS Delay(Tr rd) :
Row Cycle (Trc) :
Command Rate(CR) :
Write Recover Ti me(Twr):
> Memory Configura tion
> ECC Configuratio n
> BIOSTAR Memory I nsight
Memory Clock Mode [Auto]
Memclock Value [DDR3-800]
DRAM Timing Mode [Auto]
Performance
Memory Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 198 5-200x, American Megatre nds, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
Memory Configurati on
Bank Interleaving [Auto]
Channel Interleavi ng [XOR of Addre ss bit]
Enable Clock to Al l DIMMs [Disabled]
MemClk Tristate C3 /ATLVID [Disabled]
Memory Hole Remapp ing [Enabled]
DCT Unganged Mode [Always]
Power Down Enable [Disabled]
Page Smashing [Disabled]
Enable Bank Memo ry
Interleaving
Performance
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
performance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options: Auto (Default)

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