Supermicro SYS-5019S-MN4 — настройки BIOS для повышения производительности и безопасности [35/61]
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Supermicro SYS-5019S-MN4 — настройки BIOS для повышения производительности и безопасности [35/61]

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Supermicro SYS-5019S-MN4 Инструкция по эксплуатации онлайн [35/61] 263876
Chapter 6: BIOS
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SuperServer 5019S-MN4 User's Manual
the user with greater reliability, security and availability in networking and data-sharing. The
settings are Enabled and Disabled.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disabled
and Enabled.
Adjacent Cache Line Prefetch (Available when supported by the CPU)
Select Disabled for the CPU prefetcher to prefetch the cache line for 64 bytes. Select Enabled
for the CPU prefetcher to prefetch both cache lines for 128 bytes as comprised. The options
are Enabled and Disabled.
CPU AES
Select Enabled to enable Intel CPU Advanced Encryption Standard (AES) Instructions for
CPU to enhance data integrity. The options are Enabled and Disabled.
Boot Performance Mode
This feature allows the user to select the performance state that the BIOS will set before the
operating system handoff. The options are Power Saving, Max Non-Turbo Performance
and Turbo Performance.
HardWare P-States (HWP)
Use this feature to enable or disable hardware P-States support. The options are Disabled
and Enabled.
Intel
®
SpeedStep™
Intel SpeedStep Technology allows the system to automatically adjust processor voltage and
core frequency to reduce power consumption and heat dissipation. The options are Disabled
and Enabled.
Turbo Mode
Select Enabled for processor cores to run faster than the frequency specied by the
manufacturer. The options are Disabled and Enabled.
Package Power Limit MSR Lock
Select Enabled to lock the package power limit for the model specic registers. The op-
tions are Disabled and Enabled.
Power Limit 1 Override
Select Enabled to support average power limit (PL1) override. The default setting is
Disabled.
Power Limit 2 Override
Select Enabled to support rapid power limit (PL2) override. The default setting is Enabled.
Power Limit 2
Use this item to congure the value for Power Limit 2. The value is in milli watts and the
step size is 125mW. Use the number keys on your keyboard to enter the value. Enter 0
to use the manufacture default setting If the value is 0, the BIOS will set PL2 as 1.25*
TDP. Enter 0 to use the manufacture default setting.
1-Core Ratio Limit Override
This increases (multiplies) 1 clock speed in the CPU core in relation to the bus speed
when one CPU core is active. Press "+" or "-" on your keyboard to change the value.
Enter 0 to use the manufacture default setting.
2-Core Ratio Limit Override
This increases (multiplies) 2 clock speeds in the CPU core in relation to the bus speed
when two CPU cores are active. Press "+" or "-" on your keyboard to change the value.
Enter 0 to use the manufacture default setting.
3-Core Ratio Limit Override
This increases (multiplies) 3 clock speeds in the CPU core in relation to the bus speed
when three CPU cores are active. Press "+" or "-" on your keyboard to change the value.
Enter 0 to use the manufacture default setting.
4-Core Ratio Limit Override
This increases (multiplies) 4 clock speeds in the CPU core in relation to the bus speed
when three CPU cores are active. Press "+" or "-" on your keyboard to change the value.
Enter 0 to use the manufacture default setting.
CPU C-States
Use this feature to enable the C-State of the CPU. The options are Disabled and Enabled.
Enhanced C-States
Use this feature to enable the enhanced C-State of the CPU. The options are Disabled
and Enabled.
C-State Auto Demotion
Use this feature to prevent unnecessary excursions into the C-states to improve latency.
The options are Disabled, C1, C3, and C1 and C3.
C-State Un-Demotion
This feature allows the user to enable or disable the un-demotion of C-State. The options
are Disabled, C1, C3, and C1 and C3.

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