ASRock AB350M-HDV R3.0 [57/87] English

English

Refresh Cycle Time

e Refresh command period.

RAS to RAS Delay (tRRD_S)

e number of clocks between two rows activated in dierent banks of the same rank.

RAS to RAS Delay (tRRD_L)

e number of clocks between two rows activated in dierent banks of the same

rank.

Four Activate Window (tFAW)

e time window in which four activates are allowed the same rank.

Write to Read Delay (tWTR_S)

e number of clocks between the last valid write operation and the next read command to

the same internal bank.

Write to Read Delay (tWTR_L)

e number of clocks between the last valid write operation and the next read command to

the same internal bank.

Write Recovery Time (tWR)

e amount of delay that must elapse aer the completion of a valid write operation,

before an active bank can be precharged.

Trcpage (tMAW,MAC)

e minimum average time in memory clock cycles within a refresh window from

an activate command to another activate command.

TrdrdScL

e minimum number of cycles from the last clock of virtual CAS of the rst read-

burst operation to the clock in which CAS is asserted for a following read-burst

operation in the same chipselect in the same bank group

TwrwrScL

e minimum number of cycles from the last clock of virtual CAS of a rst write-

burst operation to the clock in which CAS is asserted for a following write-burst

operation in the same bank group.