ASRock AB350M-HDV R3.0 [59/87] Cad bus configuration

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TwrwrDd

e minimum number of cycles from the last clock of virtual CAS of the rst write-burst

operation to the clock in which CAS is asserted for a following write-burst operation in a

dierent DIMM.

TrdrdSc

e minimum number of cycles from the last clock of virtual CAS of the rst read-burst

operation to the clock in which CAS is asserted for a following read-burst operation in the

same chipselect.

TrdrdSd

e minimum number of cycles from the last clock of virtual CAS of the rst read-burst

operation to the clock in which CAS is asserted for a following read-burst operation in the

same DIMM.

TrdrdDd

e minimum number of cycles from the last clock of virtual CAS of the rst read-burst

operation to the clock in which CAS is asserted for a following read-burst operation in a

dierent DIMM.

tCKE

Species the CKE minimum high and low pulse width in memory clock cycles.

ProcODT

Species the Processor ODT

Data Bus Conguration

Congure the RttNom, RttWr and RttPark.

Gear Down Mode

Power Down Enable

CAD Bus Conguration

Command Rate (CR)

e delay between when a memory chip is selected and when the rst active command can

be issued.