Asus z170i pro gaming [57/86] Cpu core cache current limit max auto

Asus z170i pro gaming [57/86] Cpu core cache current limit max auto
ASUS Z170I PRO GAMING
2‑23
The following items appear only when you set the Turbo Mode to [Enabled].
Turbo Mode Parameters
Long Duration Package Power Limit [Auto]
Allows you to limit the Turbo Ratio’s time duration that exceeds the TDP (Thermal
Design Power) for maximum performance. Use the <+> or <‑> keys to adjust the value.
The values range from 1 W to 4096 W.
Package Power Time Window [Auto]
Also known as Power Limit 1, this item allows you to maintain the time window for
Turbo Ratio over TDP (Thermal Design Power). Use the <+> or <‑> keys to adjust the
value. The values range from 1 to 127 in seconds.
Short Duration Package Power Limit [Auto]
Also known as Power Limit 2, this item allows you to provide rapid protection when
the package power exceeds the Power Limit 1. Use the <+> or <‑> keys to adjust the
value. The values range from 1 W to 4096 W.
IA AC Load Line [Auto]
This item allows you to set the AC loadline dened in 1/100 mOhms. Use the <+> and <‑>
keys to adjust the value. Conguration options: [Auto] [0.01] ‑ [62.49]
IA DC Load Line [Auto]
This item allows you to set the DC loadline dened in 1/100 mOhms. Use the <+> and <‑>
keys to adjust the value. Conguration options: [Auto] [0.01] ‑ [62.49]
2.5.13 CPU Core/Cache Current Limit Max. [Auto]
Allows you to set a higher current limit to prevent a frequency or power throttling when
overclocking. Use the <+> or <‑> keys to adjust the value. The values range from 0.00A to
255.50A with a 0.25A interval.
2.5.14 Min. CPU Cache Ratio [Auto]
Allows you to set the minimum possible CPU cache ratio. Use the <+> or <‑> keys to adjust
the value. The values range from 0 to 83 with a 1 interval.
2.5.15 Max. CPU Cache Ratio [Auto]
Allows you to set the maximum possible CPU cache ratio. Use the <+> or <‑> keys to adjust
the value. The values range from 8 to 83 with a 1 interval.
2.5.16 Internal PLL Voltage [Auto]
Allows you to congure the offset for the Core PLL VCC Trim.

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