Tektronix MSO64 — понимание ошибок времени в DDR: tERR и tDQSCK [599/628]

tERR(n) (DDR)

tERR(n) is the cumulative error across multiple consecutive cycles from tCK(avg). It measures time difference between the sum

of clock period for a 200-cycle window to n times tCK(avg).

Where,

n = 2 for tERR(2 per)

n = 3 for tERR(3 per) and so on.

tERR(m-n) (DDR)

tERR(m-n)

tERR(m-n) is the cumulative error across multiple consecutive predefined cycles from tCK(avg). This is measured similar to

tERR(n per).

Where,

6 ≤ n ≤ 10 for tERR (6-10 per)

11 ≤ n ≤ 50 for tERR (11-50 per)

tDQSCK (DDR)

tDQSCK is the strobe output access time from differential clock. tDQSCK is measured between the rising edge of clock before or

after the differential strobe Read preamble time. The edge locations are determined by the mid-reference voltage levels.

tCKSRE

tCKSRE is the valid clock cycles required after Self Refresh Entry (SRE) command. Changing the input clock frequency or the

supply voltage is permissible only after tCKSRE time when the SRE command is registered.

Measurement algorithms

4/5/6 Series MSO Help 569