Biostar M7VIB [51/73] Chapter 2 bios setup

Biostar M7VIB [51/73] Chapter 2 bios setup
Chapter 2 BIOS Setup
2-16
PCI2 Post Write
When Enabled, CP U writes are allowed to post on the AGP bus.
The Choices: Enabled (default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification.
The Choices: Enabled (default), Disabled.
Memory Hole
When enabled, you can reserve an area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. Refer to the user documentation of
the peripheral you are installing for more information.
The Choices: Disabled (default), 15M – 16M.
System BIOS Cacheable
Selecting the “Enabled” option allows caching of the system BIOS ROM at
F0000h-FFFFFh, which can improve system performance. However, any programs
writing to this area of memory will cause conflicts and result in system errors.
The Ch o ice s: Enabled, Disabled (default).
Video RAM Cacheable
Enablin g this opt ion allows caching of the video RAM, result ing in better system
performance. However, if any program writes to this memory area, a system error
may result.
The Cho ices: Enabled, Disabled (default).

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