ASRock B650M-HDV/M.2 [36/85] Twrwrsd

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TrdrdScL

e minimum number of cycles from the last clock of virtual CAS of the rst read-

burst operation to the clock in which CAS is asserted for a following read-burst

operation in the same chipselect in the same bank group.

TrdrdSc

e minimum number of cycles from the last clock of virtual CAS of the rst read-

burst operation to the clock in which CAS is asserted for a following read-burst

operation in the same chipselect.

TrdrdSd

e minimum number of cycles from the last clock of virtual CAS of the rst read-

burst operation to the clock in which CAS is asserted for a following read-burst

operation in the same DIMM.

TrdrdDd

e minimum number of cycles from the last clock of virtual CAS of the rst read-

burst operation to the clock in which CAS is asserted for a following read-burst

operation in a dierent DIMM.

TwrwrScL

e minimum number of cycles from the last clock of virtual CAS of a rst write-

burst operation to the clock in which CAS is asserted for a following write-burst

operation in the same bank group.

TwrwrSc

e minimum number of cycles from the last clock of virtual CAS of the rst write-

burst operation to the clock in which CAS is asserted for a following write-burst

operation in the same chipselect.

TwrwrSd

e minimum number of cycles from the last clock of virtual CAS of the rst write-

burst operation to the clock in which CAS is asserted for a following write-burst

operation in the same DIMM.

TwrwrDd

e minimum number of cycles from the last clock of virtual CAS of the rst write-

burst operation to the clock in which CAS is asserted for a following write-burst

operation in a dierent DIMM.