Biostar TF8200 A2+ Версия 5.x [31/39] Tf8200 a2 bios manual

Biostar TF8200 A2+ Версия 5.x [31/39] Tf8200 a2 bios manual
TF8200 A2+ BIOS Manual
30
DRAM Timing Configuration
BIOS SETUP U TILITY
vxx.xx (C)Copyright 1985-200x, American Me gatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
DRAM Timing Configuration
Memory CLK
CAS Latency(Tcl)
RAS/CAS Delay(Trcd)
Row Precharge Time(Trp)
Min Active RAS(Tras)
RAS/RAS Delay(Trrd)
Row Cycle (Trc)
> Memory Configuration
DRAM Timing Mode [Aut o]
CAS Latency(CL) [Aut o]
2T Command [Aut o]
TRCD [Aut o]
TRP [Aut o]
tRTP [Aut o]
T-Series
Memory Configuration
BIOS SETUP U TILITY
vxx.xx (C)Copyright 1985-200x, American Me gatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
Memory Configuration
Bank Interleaving [Aut o]
Channel Interleaving [XOR of Address bit]
Enable Clock to All DIMMs [Dis abled]
MemClk Tristate C3/ATLVID [Dis abled]
Memory Hole Remapping [Ena bled]
DCT Unganged Mode [Alw ays]
Power Down Enable [Ena bled]
Power Down Mode [Cha nnel]
Enable Bank Memory
Interleaving
T-Series
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
performance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options: Auto (Default) / Disabled

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