ECS Elitegroup C51G-M2 [41/88] Using bios

ECS Elitegroup C51G-M2 [41/88] Using bios
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Using BIOS
NB SB HT Speed (4x)
K8 NB HT Width ( 16, 16 )
DRAM Configuration (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
This item enables users to set the speed of HyperTransport from the Southbridge to the
Northbridge.
This item enables users to set the HyperTransport width between CPU and the Northbridge
NB SB HT Width ( 8, 8 )
This item enables users to set the HyperTransport width between the Northbridge and the
Southbridge.
Timing Mode (Auto)
This item enables you to specify the DRAM timing mode to be configured automatically or
manually.
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommended that you leave this item at the default value. The 2T setting
requires faster memory that specifically supports this mode.
This item specifies the RAS# to CAS# delay to Rd/Wr command to the same bank.
Min RAS# active time (Tras) (8T)
This item specifies the minimus RAS# active time.
Memclock index value (Mhz) (200Mhz)
When DDR Timing Setting by is set to Manual, use this item to set the DRAM frequency.
CAS# latency (Tcl) (2.5)
RAS# to CAS# delay (Trcd) (4T)
Timing Mode [Auto]
Memlock index value (Mhz) 200Mhz
CAS# latency (Tcl) 2.5
Min RAS# active time (Tras) 8T
RAS# to CAS# delay(Trcd) 4T
Row precharge Time (Trp) 4T
User Config mode [Auto]
1T/2T Memory Timing 2T
Read Preamble value 6ns
Async Latency value 6ns
Item Help
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Menu Level
x
x
x
x
x
x
x
x

F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
Phoenix - Award WorkstationBIOS CMOS Setup Utility
DRAM Configuration

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