D-Link DWS-3160-24TC [231/505] Traffic segmentation settings

DWS-3160 Series Gigabit Ethernet Unified Switch Web UI Reference Guide

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Loopback Detection port will restart (change to normal state) when the Loopback Detection Recover Time times

out. The Loopback Detection function can be implemented on a range of ports at a time. The user may enable or

disable this function using the drop-down menu.

To view this window, click Security > Loopback Detection Settings as shown below:

Figure 11-45 Loopback Detection Settings window

The fields that can be configured are described below:

Parameter Description

Loopback Detection

State

Use the radio button to enable or disable loopback detection. The default is

Disabled.

Mode

Use the drop-down menu to toggle between Port-based and VLAN-based.

Trap State

Set the desired trap status: None, Loop Detected, Loop Cleared, or Both.

Log State

Specifies the state of the log for loopback detection.

Interval (1-32767)

The time interval (in seconds) that the device will transmit all the CTP (Configuration

Test Protocol) packets to detect a loop-back event. The valid range is from 1 to

32767 seconds. The default setting is 10 seconds.

Recover Time (0 or 60-

1000000)

Time allowed (in seconds) for recovery when a Loopback is detected. The Loop-

detect Recover Time can be set at 0 seconds, or 60 to 1000000 seconds. Entering 0

will disable the Loop-detect Recover Time. The default is 60 seconds.

From Port / To Port

Use the drop-down menus to select a range of ports to be configured.

State

Use the drop-down menu to toggle between Enabled and Disabled.

Click the Apply button to accept the changes made for each individual section.

Traffic Segmentation Settings

Traffic segmentation is used to limit traffic flow from a single or group of ports, to a group of ports. This method of

segmenting the flow of traffic is similar to using VLANs to limit traffic, but is more restrictive. It provides a method of

directing traffic that does not increase the overhead of the master switch CPU.